1. Field of the Invention
The present invention relates to a sensing detection circuit in a dynamic random access memory (DRAM) for minimizing the sensing access time in the DRAM.
2. Description of the Prior Art
FIG. 1 shows a typical memory array 1 with its associated circuit comprising a first clock signal generator CG1, a sensing clock signal generator SCG, a delay block DB and a second clock signal generator CG2.
The first clock signal generator CG1 is operative to receive an input, for example RAS or RAS and CAS for generating clock signals which operate the sensing clock signal generator SCG. The thus produced sensing signal S1 from the sensing clock signal generator SCG is applied to the memory array 1 for the sensing of bit lines sharing stored cell data in the DRAM.
To secure enough sensing time, the delay block DB has been used to delay the next clock signal from the second clock signal generator CG2 which increases the access time.